Devices such as flash memories, EEPROMs (Electrically Erasable Programmable Read Only Memories), etc., require high positive and negative voltages for modify operations (program and erase). In order to manage these high voltages, control signals of similar voltage levels are required. These control signals are generated through level shifter circuits that receive a logic level signal as an input and generate a corresponding high voltage signal as an output. A positive level shifter is a circuit that shifts the logic level input signal into corresponding higher voltage positive voltage level signals and a negative level shifter circuit shifts the logic level input signal into corresponding negative voltage level signals.
FIG. 1 illustrates a circuit diagram of a conventional high-voltage cascode switching module based negative level shifter 100. The negative level shifter 100 shifts logic level signals to generate corresponding negative voltage signals. It includes a plurality of PMOS transistors 102, 104, 106, 108, a plurality of NMOS transistors 110, 112, cross coupled PMOS transistors 114, 116, and cross coupled NMOS transistors 118, 120. The input signal is a logic level signal IN for which logic ‘1’ corresponds to VDD and logic ‘0’ corresponds to zero. The negative level shifter 100 generates four output signals at nodes OUTH, OUTHN, OUT and OUTN. Among these, the output signals at the nodes OUTH and OUTHN are complementary signals switching over the full range of voltage supplies (i.e., switching between VDD and VNEG) whereas the output signals at the nodes OUT and OUTN switch between zero and VNEG.
Voltage levels of the four output signals at the output nodes OUT, OUTN, OUTH and OUTHN for different values of the logic level input signal IN are summarized in TABLE 1.
TABLE 1INPUTOUTPUTINOUTOUTNOUTHOUTHN10VNEGVDDVNEG0VNEG0VNEGVDD
To understand the operation of the negative level shifter circuit 100, consider an initial state at time t=0, when the input signal IN=1 (VDD), OUTH=VDD, OUT=0, OUTHN=VNEG and OUTN=VNEG. As the input signal IN is switched from 1 to 0, PMOS transistor 102 is switched ON, resulting in charging of the first output node OUTHN (initially charged to VNEG) to the supply voltage VDD and subsequent charging of the third output node OUTN (initially charged to VNEG) to a voltage −Vtn (where Vtn corresponds to the threshold voltage of the NMOS transistor) through NMOS transistor 110. At this time, NMOS transistor 120 is experiencing a gate-source voltage Vgs of −Vtn−VNEG (absolute value of |VNEG|−|Vtn|), and is trying to force a VNEG voltage at fourth output node OUT. At the same time, PMOS transistor 116 is experiencing a gate-source voltage Vgs of −Vtn, and is trying to force a zero voltage at the fourth output node OUT. If Vtn>=Vtp (where Vtp corresponds to the threshold voltage of the PMOS transistor). As a result, a conflict develops between PMOS transistor 116 and NMOS transistor 120. With appropriate sizing of transistors 116 and 120, the NMOS transistor 120 is made to over-ride PMOS transistor 116 and drive voltage VNEG on the fourth output node OUT and subsequently on the second output node OUTH. As node OUT is discharged to VNEG, it eventually charges node OUTN to 0 through PMOS 116.
Limitations of the Conventional Architecture
1 High Switching Time and Switching Currents:
At the time of switching, NMOS 120 experiences a VGS of −Vtn−Vneg (in absolute values |VNEG|−|Vtn| where Vtn can be as high as 1V and operates in conflict with PMOS 116 as explained previously. This results in a large switching time and as a result a large amount of short circuit current flows for a relatively long duration of time between supplies VDD and VNEG.
2 Poor Performance at Lower Value of VDD:
At lower values of VDD, the pull up path becomes weak as compared to the pull down path owing to reduced gate-source voltages of the upper PMOS transistors and hence the performance of the level shifter circuit 100 deteriorates.
3 Not a Very Robust Design:
The design of the level shifter circuit 100 is not robust owing to 3 factors:
a) There is a conflict between the NMOS transistor 120 and the PMOS transistor 116 during switching.
b) For the case when IN=1, the N-well of the PMOS transistor 106 floats while when IN=0, the N-well of PMOS transistor 108 floats. These floating N-wells in the vicinity of negative voltages can turn-on the parasitic diode of corresponding PMOS transistors resulting in unreliable behavior (latch-up).
c) This implementation is prone to metastability owing to transiently floating nodes connected to cross-coupled transistor structures 114 with 116 and 118 with 120. Consider the transition of the level shifter from low voltage operation (when VNEG=0) to high voltage operation (when VNEG goes negative). During low voltage operation, IN=1 (say), hence OUTH=VDD and since VNEG=0, nodes OUTHN, OUTN and OUT are floating. As the level shifter circuit 100 enters in high voltage operation and VNEG goes sufficiently negative, the node OUTHN and the node OUTN discharged to VNEG and the node OUT charged to voltage zero. However, if due to mismatch in the node OUT and the node OUTN (if the node OUT is a lighter node as compared to the node OUTN), when VNEG is going negative, node OUT momentarily becomes more negative than the OUTN. In this situation, on one hand the NMOS transistor 112 tries to charge the OUT and increase its voltage level while on the other hand PMOS transistor 114 (which is ON since OUT is negative) tries to force zero on the node OUTN preventing it from going negative thereby switching on NMOS transistor 120 which tries to force negative voltage on the node OUT. This situation could result in a loop, where there is static consumption between VDD and VNEG as transistors 104, 108, 112 and 120 are all ON and could result in all the output nodes sitting at intermediate voltages for a long time, leading to metastability.
Hence, the negative level shifter 100 has a large switching time, poor performance at lower values of VDD, and is not a very robust design owing to the presence of floating nodes and its being prone to metastability.
FIG. 2 illustrates the circuit diagram of a conventional field breakdown free negative level shifting circuit 200 as described in U.S. Pat. No. 6,483,366, the disclosure of which is hereby incorporated by reference. The field breakdown free negative level shifting circuit 200 is divided into a first stage circuit 202 and a second stage circuit 204. The first stage circuit 202 includes a first voltage distributor 206 and a first driver 208. The second stage circuit 204 includes a second voltage distributor 210 and a second driver 212. The circuit 200 provides voltage switching between VDD and VNEG, where the VDD is a positive supply voltage and the VNEG is a negative voltage. The circuit 200 needs an intermediate voltage V1 between the VDD and the VNEG. The intermediate voltage V1 is selected such that no transistor is stressed. The first stage circuit 202 is switching between VDD and V1 and the second stage circuit 204 is switching between zero (GND) and VNEG. The output of the first stage circuit 202 serves as input for the second stage circuit 204. The limitation with this circuit 200 is that the intermediate voltage V1 needs to be generated and managed, and additionally there is no output node switching directly between VDD and VNEG.
FIG. 3 illustrates a circuit diagram of a conventional positive level shifter. The positive level shifter 300 shifts logic level signals to generate corresponding positive voltage signals. The positive level shifter 300 includes a plurality of NMOS transistors 302, 304, 306, 308, a plurality of PMOS transistors 310, 312, 314, 316, and cross coupled PMOS transistors 318, 320. The positive level shifter 300 receives a logic level input signal IN for which logic ‘1’ corresponds to VDD and logic ‘0’ corresponds to zero. The positive level shifter 300 generates four output signals at nodes OUTH, OUTHN, OUT and OUTN. Among these, the output signals at the nodes OUTH and OUTHN are switching between VPOS and GND whereas the output signals at the nodes OUT and OUTN are switching between VPOS and CASC+Vtp. The voltage CASC is a cascode voltage (whose value is between VPOS and zero) so chosen to prevent any transistor from getting stressed. Output voltages at the output nodes OUT, OUTN, OUTH and OUTHN for different values of the logic level input signal IN are summarized in TABLE 2.
TABLE 2INPUTOUTPUTINOUTOUTNOUTHOUTHN1VPOSCASC + VtpVPOS00CASC + VtpVPOS0VPOS
To understand the switching of the positive level shifter circuit 300, consider an initial state at time t=0, where the input signal IN=1 (VDD), OUTH=VPOS, OUT=VPOS, OUTHN=0 and OUTN=CASC+Vtp. Now, as the first input signal IN is switched from 1 to 0 and the second input signal IN_N is switched from 0 to 1, the NMOS transistor 304 is switched ON, resulting in discharging of the second output node OUTH (initially charged to VPOS) to zero and subsequently discharging of the fourth output node OUT (initially charged to VPOS) to a voltage CASC+Vtp through PMOS transistor 312. At this time, PMOS transistor 318 experiencing the source-gate voltage Vsg of VPOS−(CASC+Vtp), is charging third output node OUTN to VPOS and subsequently the first output node OUTHN is charged to VPOS through transistor 310. The voltage level at the fourth output node OUT (and OUTN for IN=1) can vary between CASC+Vtp and CASC−Vtp. This results in unreliable operation. Transistors 314 and 316, acting as diodes, are used for not allowing the voltage level to fall below CASC−Vtp and alleviate this problem to a certain extent; however this does not provide fail safe operation.
The limitations of the conventional architecture described above define the need for a level shifting circuit that provides improved switching speed and is fail-safe while over a wide range of supply voltage.